Throughout the prior art, metal gate integration has proven difficult to achieve in a conventional process flow for metal oxide semiconductor (MOS) transistors. Most metal gate materials interact with the gate dielectric during the high temperature processing needed for source/drain junction activation anneals. The need to keep the metal gate stack from receiving high temperature anneals has lead to the development of the “gate last” or “replacement gate” process for which the gate stack is fabricated last and remains below 500° C. during subsequent processing. Although the prior art replacement gate process increases the number of material choices for a metal gate, the process increases complexity and cost.
U.S. application Ser. No. 10/300,165, entitled “METHOD AND PROCESS TO MAKE MULTIPLE-THRESHOLD METAL GATE CMOS TECHNOLOGY”, filed Nov. 20, 2002, now U.S. Pat. No. 6,846,734, describes an approach for forming a metal gate silicide in a conventional CMOS transistor processing flow, in which the “replacement gate” process is not used. In this approach, the number of processing steps has been minimized, therefore keeping the complexity to a minimum and cost down. A second advantage of this approach is the ability to deposit metal using standard physical vapor deposition for forming the silicide metal gate. Since the metal is not being directly deposited on the gate dielectric there is no need for chemical vapor deposition (CVD) or atomic layer deposition (ALD), which reduces gate dielectric damage by eliminating the use of a plasma. An additional advantage is the ease of passivation of the gate dielectric after silicide metal gate formation. Hydrogen readily diffuses through the silicide allowing passivation in a conventional furnace anneal process.
Current CMOS technology uses silicides as contacts to source/drain and gate regions of the devices. Examples of silicides with low resistivity and contact resistance that are currently being used are the C54 phase of TiSi2, CoSi2, and NiSi. All three of these silicides are integrated using a self-aligned silicide process (i.e., a salicide process). This process consists of a blanket deposition of the metal (Ti, Co, or Ni) with a cap layer (such as TiN, Ti or W), annealing at a first temperature to form a first silicide phase (i.e., the C49 phase of TiSi2, CoSi, or NiSi), selectively wet etching the cap layer and unreacted metal that is not in contact with silicon, and annealing at a second temperature to form the low resistant metal silicide phase (the C54 phase of TiSi2 or CoSi2). For low resistance NiSi, the second anneal is not needed. An additional approach for the Ni silicide is to form a metal rich Ni silicide during the first anneal followed by the formation of NiSi during the second anneal. The advantage of these particular silicides is that they all may be implemented with the self-aligned process avoiding additional lithographic steps.
In future technology, silicon dioxide or silicon oxynitride dielectrics will be replaced with a gate material that has a higher dielectric constant. These materials are known as “high-k” materials with the term “high-k” denoting an insulating materials whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, hafnium oxide, hafnium silicate, or hafnium silicon oxynitride are particularly interesting as suitable replacement candidates for conventional gate dielectrics due to their excellent thermal stability at high temperature. The higher dielectric constants allow for thicker dielectric films and thus lower gate leakage currents.
The combination of a fully silicided metal gate electrodes and a high-k gate dielectric is very attractive. Fully silicided metal gate electrodes substantially eliminate the polycrystalline depletion effect and therefore result in a substantial decrease in the electrical thickness of the gate dielectric by approximately 0.4 nm to 0.7 nm. High-k dielectric materials allow for thicker gate dielectrics than conventional gate dielectric materials and therefore decrease device leakage current by orders of magnitude in comparison to devices incorporating conventional gate dielectric materials, such as SiO2 and SiOxNy. The combined benefits provide a gate stack that lowers the FETs power use (need to efficiently cool is lessened) and boosts the performance.
Unfortunately, a gate stack comprising a fully silicided metal gate electrode and a high-k gate dielectric, similar to a gate stack comprising a polycrystalline Si gate conductor and a high-k gate dielectric disadvantageously suffers from pinning of the turn on voltage, hereafter referred to as threshold voltage (Vt), for p-type field effect transistors (pFETs). The terms “pinning of the turn on voltage” denote a shift in the threshold voltage (Vt) of the device resulting from interaction between the high-k gate dielectric, such as hafnium oxide, with the gate conductor. The effect of the high-k gate dielectric on the threshold voltage (Vt) of semiconducting devices is now discussed in greater detail.
In standard silicon CMOS technology, pFETs use a boron (or other acceptor) doped p-type polysilicon layer as a gate electrode that is deposited on top of a silicon dioxide or silicon oxynitride gate dielectric layer. The gate voltage is applied through the polysilicon layer to create an inversion channel in the n-type silicon underneath the gate dielectric layer. For a pFET to work properly, the inversion should begin occurring at slightly negative voltages applied to the polysilicon gate electrode. The poly-Si/gate dielectric/n-type silicon stack forms a capacitor that swings into inversion at around 0 V and into accumulation around +1 V (depending on the substrate doping). The threshold voltage (Vt), which can be interpreted as the voltage at which the inversion starts occurring, is therefore approximately 0 V and the flatband voltage (Vfb), which is the voltage just beyond which the capacitor starts to swing into accumulation, is approximately +1 V. The exact values of the threshold and flatband voltages (Vt, Vfb) have a dependence on the doping level in the silicon substrate, and can be varied somewhat by choosing an appropriate substrate doping level.
Unfortunately, when pFETs are fabricated using high-k dielectrics, such as hafnium oxide or hafnium silicate, it is a well known problem that the flatband voltage (Vfb) of the device is shifted from its ideal position of close to about +1 V, to about 0+/−300 mV. This shift in flatband voltage (Vfb) is published in C. Hobbs et al., entitled “Fermi Level Pinning at the Poly-Si/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers. Consequently, the threshold voltage (Vt) of the device is shifted to approximately −1 V. This threshold voltage (Vt) shift is believed to be a consequence of an intimate interaction between the Hf-based gate dielectric layer and the polysilicon layer. The threshold voltage (Vt) therefore is not in the “right” place, i.e., it is too high for a useable CMOS technology.
For a fully silicided metal gate and since polysilicon is deposited on the high-k dielectric (hafnium oxide or hafnium silicate) at elevated temperatures (>600° C.), the same threshold pinning/shifting effect is operable independent of silicide formation. FIG. 1 depicts a plot of capacitance v. voltage for pFET devices having a fully silicide NiSi gate electrode on a SiOxNy gate dielectric, indicated by reference number 50, and pFET devices having a fully silicided NiSi gate electrode on a HfO2 high-k gate dielectric, indicated by reference number 55. In comparison to pFET devices comprising a SiOxNy gate dielectric and fully silicided NiSi gate electrode, the threshold voltage (Vt) of pFET devices comprising a HfO2 high-k gate dielectric and a fully silicided NiSi gate electrode is shifted approximately 230 mV. The pFETs depicted in FIG. 1 have a gate dielectric thickness on the order of about 30 nm, a doping concentration of about 1E16 cm−2 to about 5E17 cm−2, and a channel length on the order of about 50 μm.
One possible solution to the above problem of threshold voltage (Vt) shifting is by substrate engineering in which channel implants can be used to shift thresholds. Although substrate engineering is one possible means to stabilize threshold voltage (Vt) shift, it can do so to a limited extent, which is inadequate for FETs that include a gate stack comprising a silicide metal gate electrode and a hafnium-containing high-k gate dielectric.
In view of the above mentioned problem in threshold voltage (Vt) and flatband voltage shift (Vfb), it has been nearly impossible to develop a fully silicided metal gate electrode/high-k gate dielectric CMOS technology that is capable of stabilizing the threshold and flatband voltage (Vt, Vfb) for FETs. As such, a method and structure that is capable of stabilizing the threshold voltage (Vt) and flatband voltage (Vfb) of FETs containing a fully silicided metal gate electrode/high-k dielectric gate stack is needed.